Comparison ledger
Logitech 1 DP 41, STEAG Mecapol E 460, side by side. Every value shown is drawn from the cited encyclopedia entries.
| Attribute | 1 DP 41Logitech | Mecapol E 460STEAG |
|---|---|---|
| OEM | Logitech | STEAG |
| Category | CMP | CMP |
| Wafer size | — | 4" |
| Process node | — | — |
| Introduced | — | — |
| Production run | — | — |
| Lifecycle | — | — |
| Lifecycle milestones | — | — |
| Control system | — | — |
| Generation | — | — |
| Family | Logitech 1 DP 41 | STEAG Mecapol E 460 |
| Specifications | ||
| Phase | 3 Phase[1] | — |
| Configuration | 50/60 Hz[1] | — |
| Voltage | 480 V[1] | — |
| Make | Logitech[1] | — |
| Model | 1 DP 41[1] | — |
| Frequency | 50/60 Hz[1] | — |
| Current | 12 amps[1] | — |
| System type | — | semi-automatic system for polishing and planarization of wafers[2] |
| Wafer compatibility | — | 4", 6", and 8" wafers[2] |
| Other sample handling | — | other wafer sizes or chips can be processed by bonding them to a carrier wafer[2] |
| Slurry delivery | — | 2 pumps[2] |
| Conditioning system | — | ex-situ conditioning system[2] |
| Wafer size compatibility | — | 4", 6", 8"[2] |
| Slurry pumps | — | 2 pumps[2] |
| Equipment type | — | Semi-automatic CMP (chemical mechanical polishing) tool[2] |
| Wafer size | — | 4", 6", 8"[2] |
| Carrier wafer processing | — | Other wafer sizes or chips can be processed by bonding them to a carrier wafer[2] |
| Available slurries | — | 30N50, 30H50, 40EA50[2] |
| Oxide polishing target | — | Thermal oxide thickness range less than 500 A; removal rate 2600–2800 A/min; removal rate can be 2 to 5 times higher on deposited oxides[2] |
| Silicon polishing | — | Global removal around 8 to 10 µm for 10 min[2] |
| Consumable sets | — | Two sets: one for microelectronic layers polishing and one for copper polishing[2] |
| Microelectronic compatibility | — | Not a micro-electronic compatible tool[2] |
| Wafer size support | — | 4", 6", 8"[2] |
| Conditioning type | — | ex-situ[2] |
| Tool type | — | semi-automatic[2] |
| Type | — | semi-automatic system[2] |
| Process | — | polishing and planarization of wafers[2] |